A typical solid-state memory device has multiple memory cells coupled to bit lines that facilitate the extraction of data stored in memory cells, the extracted data to be presented at an output of the device. When data is to be read from a cell, the cell is activated and a transistor in the cell (generally referred to as an access transistor) will or will not change a pre-established voltage on the bit line depending on the data stored in the active cell. Because transistors in the memory cells are typically very small and thus are weak, and generally each bit-line is coupled to hundreds of other (inactive) cells resulting in each bit-line having significant capacitive loading, the amount of change in bit-line voltage during a defined time period is relatively small. To determine what data value the active cell is storing, each bit-line has attached thereto a sense amplifier that amplifies any change in the bit-line voltage and “slices” the amplified voltage change to produce at an output of the sense amplifier a binary one or zero. The output of the sense amplifier is then coupled to the output of the memory for use in the apparatus using the memory device, e.g., a computer.
Bit-lines are of two types: differential and single-ended. Differential bit-lines are less susceptible to induced noise than single-ended bit-lines but a memory having differential bit-lines requires twice the number of bit-line conductors compared to a memory with single-ended bit-lines and a concomitant increase in memory complexity and area. However, a memory with differential bit lines might have the fastest memory access time (used here as the time required for the memory to present data at its output measured from when an address is first applied to the memory and the memory enabled) but can only be used where a memory cell has differential outputs, e.g., static random access memory (SRAM). For those memory devices having non-differential output memory cells, single-ended bit-lines are used, such as in a read-only memory (ROM), electrically-programmable memory (e.g., EEPROM, FLASH, etc.), or a dynamic random access memory (DRAM). However, some memory designs, which would otherwise use differential bit-lines, might instead use single-ended bit-lines to save area and power when short access time is not an overriding requirement.